The present invention relates to assembled structure and assembling process of a semiconductor device, and more specifically to structure and process for a power semiconductor device using electrodes on both sides of a semiconductor wafer and requiring low power consumption.
Bipolar transistor, thyristor, DMOS and IGBT are some examples used as a semiconductor device capable of handling high power. In any case, an important requirement is to reduce power consumption by reducing the on resistance of the semiconductor device, that is the device's resistance in the operating state.
FIG. 17 schematically shows a section of a packaged semiconductor device. In FIG. 17, RW is a resistance of a bonding wire 100, RM is a resistance of a topside pad electrode layer 5, Ra is a resistance of an active semiconductor layer 4 of the semiconductor device, RSi is a resistance of a substrate layer 3 in a semiconductor wafer, RM' is a resistance of a backside metallization electrode 6, RS is a resistance of a solder 11, and RF is a resistance of a lead frame 12. The on resistance of the packaged device is the sum of these individual resistances. Ra and RSi are the components of the semiconductor layers, and all the others are the metallic components. The metallic layers and wire are all essential for the electrical connection. Ra of the active layer 4 is inherent in the semiconductor device. On the other hand, the substrate layer 3 parasitically interposes its resistance RSi in the current path of the semiconductor device. The resistance RSi of the substrate layer 3 is low especially in a wafer for a power semiconductor device. However, a semiconductor is incommensurably higher in resistivity than a metal, and low in heat conductivity. Therefore, reduction of the resistance RSi by reducing the thickness of the substrate layer 3 is remaining measures to reduce the on resistance and hence the power consumption of the semiconductor device.
A widely used conventional packaging process includes a first step of grinding a semiconductor wafer from the backside, a second step of diving the wafer into chips, a third step of bonding one chip to a lead frame, and a fourth step of electrically connecting a pad electrode on the chip to a terminal of the lead frame by wire bonding. However, the wafer becomes more difficult to handle as the wafer thickness is reduced by the backgrinding step. A recent trend toward a larger wafer increases this difficulty. As a result, the reduction of wafer thickness sharply decreases the yield rate of wafers, as shown in FIG. 18. Furthermore, a recent demand for a higher power handling capability tends to increase the size of a chip, and the fragility of a larger chip causes another problem. Thus, reduction of wafer thickness and improvement of production yield are two conflicting requirements.